1. Technical Field
The present invention generally relates to a structure and manufacturing of a power semiconductor device, and more particularly relates to a split gate planar power semiconductor field effect transistor (FET).
2. Related Art
The present invention will be illustrated in an n channel power FET, but it will be understood in the following description that the present invention is similarly applicable to a p channel power FET. In the specification of the present invention, heavily doped n-type regions are labeled as n+, and heavily doped p-type regions are labeled as p+. These heavily doped regions generally have a doping concentration between 1×1018 cm−3 and 1×1021 cm−3. In the specification of the present invention, lightly doped n-type regions are labeled as n−, and lightly doped p-type regions are labeled as p−. These lightly doped regions generally have a doping concentration between 1×1013 cm−3 and 1×1017 cm−3.
The power MOSFET has been widely used in switching applications. A high switching speed is needed to reduce the switching power loss and the sizes of passive components in a system. Thus, the object of the present invention is to provide a split gate power MOSFET with high switching speed.
In addition, the high switching speed is also needed in an IGBT structure. Therefore, another object of the present invention is to provide a split gate IGBT with high switching speed.